01 — Layout
The gate pattern
Crop a lithographic GDS/DXF layout to the area of interest and read off the polygons that define every gate.
Layout-backed electrostatics
TEMPURA
From a gate layout to the electrostatic landscape it carves into a semiconductor quantum device — meshed, solved, and ready to tune.
Tempura rasterizes a lithographic layout, stacks it with dielectrics and a quantum region, and solves the Poisson problem once. Because the solve is linear, every voltage configuration is a superposition of pre-solved basis fields.
The pipeline · interactive tour coming online
02 — Device
The 3D stack
Deposit those gates over dielectrics and a quantum region to assemble the full heterostructure in three dimensions.
03 — Potential
The live field
Solve one basis potential per gate, then tune voltages and watch the electrostatic landscape in the 2DEG respond — in real time.