Tempura
Layout-backed electrostatics

TEMPURA

From a gate layout to the electrostatic landscape it carves into a semiconductor quantum device — meshed, solved, and ready to tune.

Tempura rasterizes a lithographic layout, stacks it with dielectrics and a quantum region, and solves the Poisson problem once. Because the solve is linear, every voltage configuration is a superposition of pre-solved basis fields.

// the pipeline

One device, three steps

Scroll through the triple quantum dot — from its lithographic gate pattern to a field you can tune by hand.

01 — Layout

The gate pattern

A lithographic GDS/DXF layout is cropped to the area of interest and rasterized onto the simulation grid. Each polygon below is one gate's footprint — the metal that will shape the field.

Reading layout…
02 — Device

The 3D stack

Those gates are deposited over dielectrics and a quantum region to assemble the full heterostructure in three dimensions. Drag to orbit; hover a layer to read its cell index and z-extent.

Building stack…
drag to orbit
03 — Potential

The live field

One basis potential is solved per gate. Drag a slider and the electrostatic landscape in the 2DEG responds instantly — every configuration is a live superposition V·basis, with no solver in the browser. Form a dot, raise a barrier, see it move.

Build this device from scratch — the worked example →

Loading device…
Solving eigenstates…